SP973T8

5

Clock Input (Fig.6)

The SP973T8 will operate at clock frequencies up to and

above 30MHz. The clock input has been designed to accept

a 1Vpp signal, in either differential or single-ended mode,

sink 800

µA or source 3.2mA of current, respectively.

(See Fig.6).

decoupled to ground so that this input will then self-bias at

coupled applications as shown in Fig.8.

Alternatively a TTL level clock may be used by inserting an

appropriate value resistor in series with the coupling

capacitor.

TIMING (Fig.7)

The analog input is sampled by the SP973T8

to the pipeline operation of the device, a further one clock cycle

is required to produce the output data. As shown in Fig.7, the

output has a good data valid time, enabling the data to be

latched at both the rising and falling edges of the clock.

However, for clock frequencies above 25MHz the clock-to-

output delay time may lead to an inadequate data set up time

relative to the rising clock edge and it is therefore

recommended that the output data is latched on the falling

clock edge.

SAMPLE

N

SAMPLE

N+1

SAMPLE

N+2

SAMPLE

N+3

VIN

tAD

DATA VALID N

DATA VALID N+1

DATA VALID N-1

DATA VALID N-2

PIPELINE DELAY

4V

0V

DATA

OUTPUT

tD

CLOCK

tpw0

tpw1

tCYC

Fig.7 Timing diagram

800µA

800µA

CLOCK

INPUT

450

450

600

+5V

DIFF

CLOCK

3.8V

AGND

CLOCK

OR BIAS

DECOUPLE

AVCC

Fig.6 Clock input stage