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LT6001IMS8 Datasheet(PDF) 11 Page - Linear Technology |
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LT6001IMS8 Datasheet(HTML) 11 Page - Linear Technology |
11 / 20 page LT6000/LT6001/LT6002 11 600012fa Q1 Q17 Q6 Q2 Q10 C1 Q3 IN+ Q8 Q19 Q20 R1 R8 7M R6 R7 R2 30k D3 V+ V+ V– R4 R5 IN– R3 30k Q9 Q11 Q14 V+ OUT V– SHDN V– Q15 CM Q13 COMPLEMENTARY DRIVE GENERATOR Q12 Q4 Q5 Q7 Q16 Q18 APPLICATIO S I FOR ATIO Supply Voltage The positive supply of the LT6000/LT6001/LT6002 should be bypassed with a small capacitor (about 0.01 µF) within an inch of the pin. When driving heavy loads, an additional 4.7 µF electrolytic capacitor should be used. When using split supplies, the same is true for the negative supply pin. Rail-to-Rail Characteristics The LT6000/LT6001/LT6002 are fully functional for an input signal range from the negative supply to the positive supply. Figure 1 shows a simplified schematic of the amplifier. The input stage consists of two differential amplifiers, a PNP stage Q3/Q6 and an NPN stage Q4/Q5 that are active over different ranges of the input common mode voltage. The PNP stage is active for common mode voltages, VCM, between the negative supply to approxi- mately 1V below the positive supply. As VCM moves closer towards the positive supply, the transistor Q7 will steer Q2’s tail current to the current mirror Q8/Q9, activating the NPN differential pair. The PNP pair becomes inactive for the rest of the input common mode range up to the positive supply. The second stage is a folded cascode and current mirror that converts the input stage differential signals into a single ended output. Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain bandwidth of the amplifier. The comple- mentary drive generator supplies current to the output transistors that swing from rail to rail. Input The input bias current depends on which stage is active. The input bias current polarity depends on the input common mode voltage. When the PNP stage is active, the input bias currents flow out of the input pins. They flow in the opposite direction when the NPN stage is active. The offset error due to the input bias currents can be minimized by equalizing the noninverting and inverting source impedance. Figure 1 SI PLIFIED SCHE ATIC |
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