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MPC8560PXALFB Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MPC8560PXALFB Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 108 page  MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 3 Overview — Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller — Handles serial protocols and virtual DMA. — Three full-duplex fast serial communications controllers (FCCs) that support the following protocols: – ATM protocol through UTOPIA interface (FCC1 and FCC2 only) – IEEE802.3/Fast Ethernet – HDLC – Totally transparent operation — Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces — Four full-duplex serial communications controllers (SCCs) that support the following protocols: – High level/synchronous data link control (HDLC/SDLC) – LocalTalk (HDLC-based local area network protocol) – Universal asynchronous receiver transmitter (UART) – Synchronous UART (1x clock mode) – Binary synchronous communication (BISYNC) – Totally transparent operation — Serial peripheral interface (SPI) support for master or slave —I2C bus controller — Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats: – T1/CEPT lines –T3/E3 – Pulse code modulation (PCM) highway interface – ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers — General-purpose parallel ports—16 parallel I/O lines with interrupt capability — Supports inverse muxing of ATM cells (IMA) • 256 Kbyte L2 cache/SRAM — Can be configured as follows – Full cache mode (256-Kbyte cache). – Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks) – Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM) — Full ECC support on 64-bit boundary in both cache and SRAM modes |
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