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SO-720-LPF-GAN Datasheet(PDF) 2 Page - Vectron International, Inc |
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SO-720-LPF-GAN Datasheet(HTML) 2 Page - Vectron International, Inc |
2 / 7 page SO-720 SAW Clock Oscillator Vectron International, 267 Lowell Rd, Hudson NH 03051-4916 Tel: 1-88-VECTRON-1 Website: www.vectron.com Page 2 of 7 Rev: 21 Jun 2006 Electrical Performance Parameter Symbol Minimum Typical Maximum Units Notes Frequency Nominal Frequency Frequency Stability (Ordering Option) Aging fN fSTAB 150 ±50, ±100 800 10 MHz ppm ppm 1,2 1,2 6,8 Supply Voltage Current (No Load) VCC ICC 2.97 3.3 55 3.63 70 V mA 2,3 3 Outputs Mid Level - LVPECL Swing – LVPECL Mid Level - LVDS Swing – LVDS Current Rise Time Fall Time Symmetry Jitter (12 kHz – 20 MHz BW) 622.08 MHz Jitter (50 kHz – 80 MHz BW) 622.08 MHz IOUT tR tF SYM φJ φJ Vcc-1.4 450 VCC-2.4 250 45 Vcc-1.25 600 Vcc-2.3 350 50 0.100 0.120 Vcc-1.0 750 VCC-2.5 450 20 500 500 55 0.250 0.300 V mV-pp V mV-pp mA ps ps % ps-rms ps-rms 2,3 2,3 2,3 2,3 6 5,6 5,6 2,3 6,7 6,7 Period Jitter, RMS (622.08 MHz) φJ 2.5 3.0 ps-rms 9 Period Jitter, Peak - Peak (622.08 MHz) φJ 16 24 ps pk-pk 9 Operating Temp. (Ordering Option) TOP 0/70,-20/70 or -40/85 °C 1 Package Size 5.0 x 7.5 x 2.0 mm 1. See Standard Frequencies and Ordering Information (Pg 7). 2. Parameters are tested with production test circuit below (Fig 1). 3. Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature. 4. Measured as the maximum deviation from the best straight-line fit, per MIL-0-55310. 5. Measured from 20% to 80% of a full output swing (Fig 2). 6. Not tested in production, guaranteed by design, verified at qualification. 7. Integrated across stated bandwidth per GR-253-CORE Issue3. 8. Aging Rate for 10 years (Aging is not part of overall frequency stability budget unless specified at time of order) 9. Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 250K samples taken. Figure 1. Test Circuit Figure 2. 10K LV-PECL Waveform Vcc - 1.6V Vcc - 1.3V Vcc - 1.0V 80% 20% tR tF tA tB SYM = 100 x tA / tB 1 2 3 6 5 4 50 Ω 50 Ω Test Circuit Notes: 1) To Permit 50 Ω Measurement of Outputs, all DC Inputs are Biased Down 1.3V. 2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise. 3) 50 Ω Terminations are Within Test Equipment. (-1.3V, +2.0V) No connect (-1.3V) (+2.0V) COutput Output Enable, Disable |
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