that OOB signaling is transmitted through the MAX3786

(see Table 1). The time for the LOS circuit to detect an

inactive input and disable the associated output, or

detect an active input and enable the output, is less

than 5ns.

Equalization and Preemphasis

High-speed inputs IN0 and IN1 have integrated equal-

ization, and high-speed outputs OUT0 and OUT1 have

integrated PE to mitigate the effects of intersymbol

interference in an FR-4 transmission line signal path.

These circuits provide EQ or PE that matches the typi-

cal path loss of a 20in, 6-mil FR-4 differential stripline.

Four active-low LVCMOS inputs, EQ0EN, EQ1EN,

PE0EN, and PE1EN are provided to enable EQ and PE

independently. All four control lines are internally pulled

high through 40k

Ω resistors (see the Functional

Diagram). EQ and PE should be enabled when the total

path loss exceeds approximately 2.5dB.

Input Terminations

All high-speed inputs accept current-mode logic (CML)

and are SATA compatible. The inputs contain internal

100

Ω differential termination, and must be AC-coupled

to the controller IC and SATA-compatible disk drive for

proper operation.

Two pins (CM0 and CM1) provide access to the IN0

and IN1 common-mode points. CM0 and CM1 are nor-

mally left unconnected; however, a capacitor up to

providing a low-impedance AC common-mode path to

Output Terminations

The MAX3786 uses CML for its high-speed outputs.

They are SATA compatible and provide 50

Ω termina-

must be AC-coupled to the controller IC and SATA-

compatible disk drive for proper operation.

Applications Information

Hot Swap

The MAX3786 is designed so that arbitrary sequencing

operation of the part.

Exposed-Pad Package

QFN package with EP for signal integrity and place-

ment flexibility. The exposed pad provides thermal and

electrical connectivity to the IC, and must be soldered

to a high-frequency ground plane. It is recommended

to use at least nine vias to connect the ground pad

underneath the 32-lead thin QFN package to the PC

board ground plane.

Layout Considerations

Use controlled-impedance transmission lines to inter-

face with the MAX3786 high-speed inputs and outputs.

Power-supply decoupling capacitors should be placed

1.5Gbps Serial ATA-Compatible Mux/Buffer with

Loopback and Equalization

6

_______________________________________________________________________________________

MAX3786

IN_+

CM_

IN_-

50

Ω

50

Ω

2pF

0.2mA

1.6k

Ω

Figure 1. Input Structure (IN0, IN1)

50

Ω

50

Ω

OUT_+

OUT_-

MAX3786

Figure 2. Output Structure (OUT0, OUT1)