7

2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L128L18F_2.p65 – Rev. 6/01

©2000, Micron Technology, Inc.

2Mb: 128K x 18, 64K x 32/36

FLOW-THROUGH SYNCBURST SRAM

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)

FUNCTION

GW#

BWE#

BWa#

BWb#

BWc#

BWd#

READ

H

H

X

X

X

X

READ

H

L

H

H

H

H

WRITE Byte “a”

HL

LH

H

H

WRITE All Bytes

H

LLLL

L

WRITE All Bytes

L

X

X

X

X

X

NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.

PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)

FUNCTION

GW#

BWE#

BWa#

BWb#

READ

H

H

X

X

READ

H

L

H

H

WRITE Byte “a”

HL

LH

WRITE Byte “b”

HLHL

WRITE All Bytes

H

L

L

L

WRITE All Bytes

L

X

X

X