5

2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L128L18F_2.p65 – Rev. 6/01

©2000, Micron Technology, Inc.

2Mb: 128K x 18, 64K x 32/36

FLOW-THROUGH SYNCBURST SRAM

TQFP PIN DESCRIPTIONS

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

37

37

SA0

Input

Synchronous Address Inputs: These inputs are registered and must

36

36

SA1

meet the setup and hold times around the rising edge of CLK.

32-35, 44-49,

32-35, 44-49,

SA

80-82, 99,

81, 82, 99,

100

100

93

93

BWa#

Input

Synchronous Byte Write Enables: These active LOW inputs allow

94

94

BWb#

individual bytes to be written and must meet the setup and hold

–

95

BWc#

times around the rising edge of CLK. A byte write enable is LOW

–

96

BWd#

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb. For the x32 and x36 versions, BWa# controls DQa pins and

DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. Parity is only

available on the x18 and x36 versions.

87

87

BWE#

Input

Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold times around the

rising edge of CLK.

88

88

GW#

Input

Global Write: This active LOW input allows a full 18-, 32-, or 36-bit

WRITE to occur independent of the BWE# and BWx# lines and must

meet the setup and hold times around the rising edge of CLK.

89

89

CLK

Input

Clock: This signal registers the address, data, chip enable, byte

write enables and burst control inputs on its rising edge. All

synchronous inputs must meet setup and hold times around the

clock’s rising edge.

98

98

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable

the device and conditions the internal use of ADSP#. CE# is sampled

only when a new external address is loaded.

92

92

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

97

97

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

86

86

OE#

Input

Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

83

83

ADV#

Input

Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after

the external address is loaded. A HIGH on this pin effectively causes

wait states to be generated (no address advance). To ensure use of

correct address during a WRITE cycle, ADV# must be HIGH at the

rising edge of the first clock after an ADSP# cycle is initiated.

84

84

ADSP#

Input

Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

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