1

2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L128L18F_2.p65 – Rev. 6/01

©2000, Micron Technology, Inc.

2Mb: 128K x 18, 64K x 32/36

FLOW-THROUGH SYNCBURST SRAM

SRAM

FEATURES

• Fast clock and OE# access times

• Separate +3.3V or +2.5V isolated output buffer

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down

• 100-pin TQFP package

• Low capacitive bus loading

• x18, x32, and x36 versions available

OPTIONS

MARKING

• Timing (Access/Cycle/MHz)

6.8ns/8.0ns/125 MHz

-6.8

7.5ns/8.8ns/113 MHz

-7.5

8.5ns/10ns/100 MHz

-8.5

10ns/15ns/66 MHz

-10

• Configurations

3.3V I/O

128K x 18

MT58L128L18F

64K x 32

MT58L64L32F

64K x 36

MT58L64L36F

2.5V I/O

128K x 18

MT58L128V18F

64K x 32

MT58L64V32F

64K x 36

MT58L64V36F

• Packages

100-pin TQFP

T

• Operating Temperature Range

Commercial (0°C to +70°C)

None

Part Number Example:

MT58L64L36FT-8.5

MT58L128L18F, MT58L64L32F,

MT58L64L36F; MT58L128V18F,

MT58L64V32F, MT58L64V36F

GENERAL DESCRIPTION

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x

18, 64K x 32, or 64K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock

input (CLK). The synchronous inputs include all ad-

dresses, all data inputs, active LOW chip enable (CE#),

two additional chip enables for easy depth expansion

(CE2, CE2#), burst control inputs (ADSC#, ADSP#,

ADV#), byte write enables (BWx#) and global write

(GW#).

Asynchronous inputs include the output enable

(OE#), snooze enable (ZZ) and clock (CLK). There is also

a burst mode pin (MODE) that selects between inter-

leaved and linear burst modes. The data-out (Q), en-

abled by OE#, is also asynchronous. WRITE cycles can

be from one to two bytes wide (x18) or from one to four

bytes wide (x32/x36), as controlled by the write control

inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

**JEDEC-standard MS-026 BHA (LQFP).

100-Pin TQFP**