8

2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L128L18F_2.p65 – Rev. 6/01

©2000, Micron Technology, Inc.

2Mb: 128K x 18, 64K x 32/36

FLOW-THROUGH SYNCBURST SRAM

TRUTH TABLE

OPERATION

ADDRESS CE# CE2# CE2

ZZ

ADSP# ADSC# ADV# WRITE# OE#

CLK

DQ

USED

Deselected Cycle, Power-Down

None

H

X

X

L

X

L

X

X

X

L-H

High-Z

Deselected Cycle, Power-Down

None

L

X

L

L

L

X

X

X

X

L-H

High-Z

Deselected Cycle, Power-Down

None

L

H

X

L

L

X

X

X

X

L-H

High-Z

Deselected Cycle, Power-Down

None

L

X

L

L

H

L

X

X

X

L-H

High-Z

Deselected Cycle, Power-Down

None

L

H

X

L

H

L

X

X

X

L-H

High-Z

SNOOZE MODE, Power-Down

None

X

X

X

H

X

X

X

X

X

X

High-Z

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

H

L-H

High-Z

WRITE Cycle, Begin Burst

External

L

L

H

L

H

L

X

L

X

L-H

D

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

H

L-H

High-Z

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

High-Z

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

High-Z

WRITE Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

WRITE Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L-H

High-Z

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L-H

High-Z

WRITE Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

WRITE Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.

2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW or

GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.

3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc

pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions.

DQPc and DQPd are only available on the x36 version.

4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held

HIGH throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing

diagram for clarification.