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UG33 Datasheet(PDF) 5 Page - ATMEL Corporation |
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UG33 Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 7 page UG Series 5–5 Rev. B – 25 May. 98 Derating Factors: tP = KP x Kt x KV x tNOMINAL Process Process Best Nominal Worst KP 0.82 1.00 1.28 Ambient Temperature _C TA –55 –40 0 25 70 85 125 KT 0.74 0.79 0.92 1.00 1.15 1.20 1.32 Supply Voltage VDD 2.7 3 3.13 3.3 3.47 3.6 4 4.5 4.75 5 5.25 5.5 KV 1.89 1.66 1.58 1.49 1.41 1.35 1.23 1.1 1.05 1 0.96 0.93 External Timing Characteristics (Over the Operating Range) These timing parameters are provided for information only. Actual pin-to-pin timing characteristics guaranteed for ULCs are determined by the original FPGA or PLD data sheet plus any specific parameters that are agreed to separately by Atmel Wireless & Microcontrollers. Max Parameter Symbol Base Part SSO Min Typ Max Unit UG01 5.0 7.5 UG04–UG09 6.0 9.0 Propagation Time tPD UG14–UG20 7.0 10.5 UG33–UG90 8.5 13.0 UG120–UG140 9.5 14.5 UG01 32 6.5 10.0 UG04–UG09 50 7.5 11.5 Clock Delay Time tCO UG14–UG20 100 8.5 13.0 UG33–UG90 220 10.0 15.0 ns UG120–UG140 300 11.0 16.5 Hold Time tH 0.0 UG01 32 6.5 10.0 UG04–UG09 50 7.5 11.5 Output Enable Time tEN UG14–UG20 100 8.5 13.0 UG33–UG90 220 10.0 15.0 UG120–UG140 300 11.0 16.5 |
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Similar Description - UG33 |
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