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PI7C8150ANDE Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
7 / 111 page PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 7 of 111 APRIL 2006 – Revision 1.1 10.1 GPIO CONTROL REGISTERS............................................................................................... 70 10.2 SECONDARY CLOCK CONTROL........................................................................................ 70 10.3 LIVE INSERTION ................................................................................................................... 72 11 PCI POWER MANAGEMENT .......................................................................... 72 12 RESET ................................................................................................................... 73 12.1 PRIMARY INTERFACE RESET ............................................................................................ 73 12.2 SECONDARY INTERFACE RESET...................................................................................... 74 12.3 CHIP RESET............................................................................................................................ 74 13 SUPPORTED COMMANDS............................................................................... 74 13.1 PRIMARY INTERFACE ......................................................................................................... 74 13.2 SECONDARY INTERFACE................................................................................................... 76 14 CONFIGURATION REGISTERS...................................................................... 77 14.1 CONFIGURATION REGISTER ............................................................................................. 77 14.1.1 VENDOR ID REGISTER – OFFSET 00h......................................................................... 78 14.1.2 DEVICE ID REGISTER – OFFSET 00h .......................................................................... 78 14.1.3 COMMAND REGISTER – OFFSET 04h .......................................................................... 78 14.1.4 STATUS REGISTER – OFFSET 04h ................................................................................ 79 14.1.5 REVISION ID REGISTER – OFFSET 08h ...................................................................... 80 14.1.6 CLASS CODE REGISTER – OFFSET 08h....................................................................... 80 14.1.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 80 14.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 80 14.1.9 HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 81 14.1.10 PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 81 14.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 81 14.1.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 81 14.1.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 81 14.1.14 I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 81 14.1.15 I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 82 14.1.16 SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 82 14.1.17 MEMORY BASE REGISTER – OFFSET 20h .............................................................. 83 14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 83 14.1.19 PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 83 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 84 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ....................................................................................................................................... 84 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch....................................................................................................................................... 84 14.1.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 84 14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 85 14.1.25 ECP POINTER REGISTER – OFFSET 34h................................................................. 85 14.1.26 INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 85 14.1.27 INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 85 14.1.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 85 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 87 14.1.30 ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 88 14.1.31 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 88 14.1.32 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 89 06-0057 |
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