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PI7C8150ANDE Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
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8 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 8 of 111 APRIL 2006 – Revision 1.1 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch .......................................................................................................................................... 89 14.1.34 UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 89 14.1.35 UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 90 14.1.36 UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h .......................................................................................................................................... 90 14.1.37 UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET 58h .......................................................................................................................................... 90 14.1.38 P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 90 14.1.39 GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 91 14.1.40 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 92 14.1.41 P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 92 14.1.42 PORT OPTION REGISTER – OFFSET 74h ................................................................ 93 14.1.43 RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 95 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 95 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 95 14.1.46 CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 95 14.1.47 NEXT POINTER REGISTER – OFFSET B0h ............................................................. 95 14.1.48 SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 96 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 96 14.1.50 CAPABILITY ID REGISTER – OFFSET DCh............................................................. 96 14.1.51 NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 96 14.1.52 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 96 14.1.53 POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 97 14.1.54 CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 97 14.1.55 NEXT POINTER REGISTER – OFFSET E4h ............................................................. 97 15 BRIDGE BEHAVIOR .......................................................................................... 97 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES........................................................... 98 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ................................ 98 15.2.1 MASTER ABORT................................................................................................................ 98 15.2.2 PARITY AND ERROR REPORTING ................................................................................ 98 15.2.3 REPORTING PARITY ERRORS ....................................................................................... 99 15.2.4 SECONDARY IDSEL MAPPING ...................................................................................... 99 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ..................................... 99 16.1 BOUNDARY SCAN ARCHITECTURE................................................................................. 99 16.1.1 TAP PINS .......................................................................................................................... 100 16.1.2 INSTRUCTION REGISTER ............................................................................................ 100 16.2 BOUNDARY SCAN INSTRUCTION SET .......................................................................... 101 16.3 TAP TEST DATA REGISTERS............................................................................................ 102 16.4 BYPASS REGISTER ............................................................................................................. 102 16.5 BOUNDARY-SCAN REGISTER.......................................................................................... 102 16.6 TAP CONTROLLER .............................................................................................................102 17 ELECTRICAL AND TIMING SPECIFICATIONS....................................... 106 17.1 MAXIMUM RATINGS ......................................................................................................... 106 17.2 DC SPECIFICATIONS ..........................................................................................................106 17.3 AC SPECIFICATIONS .............................................................................................................. 107 17.4 66MHZ TIMING.................................................................................................................... 108 17.5 33MHZ TIMING.................................................................................................................... 108 17.6 POWER CONSUMPTION .................................................................................................... 108 06-0057 |
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