 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DSP56F827 Datasheet(PDF) 10 Page - Motorola, Inc |
|
||||||||||||||||||||||||||||||
DSP56F827 Datasheet(HTML) 10 Page - Motorola, Inc |
|
|
10 / 44 page  10 DSP56F826 Preliminary Technical Data IRQA 32 Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. IRQB 33 Input External Interrupt Request B—The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level- sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. MISO GPIOF6 86 Input/Output Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. After reset, the default state is MISO. MOSI GPIOF5 85 Input/Output Input/Output SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. PS 29 Output Program Memory Select—PS is asserted low for external program memory access. RD 26 Output Read Enable—RD is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the DSP data bus. When RD is deasserted high, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When a pn is owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. Signal Name Pin No. Type Description |
Similar Part No. - DSP56F827 |
|
Similar Description - DSP56F827 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
