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MT9160BN Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc |
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MT9160BN Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc |
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9 / 30 page  Advance Information MT9160B/61B 87 Figure 7a - D-Channel 16 kb/s Operation Figure 7b - IRQ Timing Diagram Figure 7c - D-Channel 8 kb/s Operation n-3 n-2 n-1 n n+1 n+2 n+3 n+4* Microport Read/Write Access D0 D1 I D2 D3 II D4 D5 III D6 D7 IV D0 D1 I D2 D3 II D4 D5 III D6 D7 IV Di-bit Group Transmit D-Channel No preset value Power-up reset to 1111 1111 * note that frame n+4 is equivalent to frame n of the next cycle. IRQ FP DSTo/ DSTi Di-bit Group Receive D-Channel Microport Read/Write Access tir =500 nsec max Rpullup= 10 k tif =500 nsec max D0 D1 Reset coincident with Read/Write of Address 04 Hex or next FP, whichever occurs first FP C4i C2 IRQ 8 kb/s operation 16 kb/s operation DSTo/ DSTi n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 II D1 III D2 IV D3 V D4 VI D5 VII D6 VIII D7 I D0 II D1 III D2 IV D3 V D4 VI D5 VII D6 VIII D7 I D0 No preset value Di-bit Group Receive D-Channel Power-up reset to 1111 1111 IRQ FP Microport Read/Write Access D-Channel Di-bit Group Transmit D-Channel |
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