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HYB18T512800AF-3.7 Datasheet(PDF) 11 Page - Infineon Technologies AG |
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HYB18T512800AF-3.7 Datasheet(HTML) 11 Page - Infineon Technologies AG |
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11 / 117 page  Data Sheet 11 Rev. 1.3, 2005-01 09112003-SDM9-IQ3P 512-Mbit DDR2 SDRAM DDR2 SDRAM HYB18T512400AF HYB18T512800AF HYB18T512160AF 1 Overview This chapter gives an overview of the 512-Mbit DDR2 SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit DDR2 SDRAM offers the following key features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O • DRAM organisations with 4, 8 and 16 data in/outputs • Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation •CAS Latency: (2), 3, 4 and 5 • Burst Length: 4 and 8 • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. • DLL aligns DQ and DQS transitions with clock •DQS can be disabled for single-ended data strobe operation • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • Data masks (DM) for write data • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. • Auto-Precharge operation for read and write bursts • Auto-Refresh, Self-Refresh and power saving Power-Down modes • Average Refresh Period 7.8 µs • Full and reduced Strength Data-Output Drivers • 1K page size for ×4 & ×8, 2K page size for ×16 • Packages: P-TFBGA-60 for ×4 & ×8 components P-TFBGA-84 for ×16 components • RoHS Compliant Products1) 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Table 1 High Performance DDR667 Product Type Speed Code –3 –3S Unit Speed Grade DDR2–667C 4–4–4 DDR2–667D 5–5–5 — max. Clock Frequency @CL5 f CK5 333 333 MHz @CL4 f CK4 333 266 MHz @CL3 f CK3 200 200 MHz min. RAS-CAS-Delay t RCD 12 15 ns min. Row Precharge Time t RP 12 15 ns min. Row Active Time t RAS 45 45 ns min. Row Cycle Time t RC 57 60 ns |
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