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XPC850SRZT80B Datasheet(PDF) 3 Page - Motorola, Inc |
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XPC850SRZT80B Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 68 page MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 3 Part II Features Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among those components: Figure 1. MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850: • Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution System Interface Unit Memory Controller Bus Interface Unit System Functions Real-Time Clock PCMCIA Interface Bus Embedded 2-Kbyte I-Cache MMU 1-Kbyte D-Cache Data MMU Load/Store Instruction Bus Parallel I/O Baud Rate Generators Dual-Port RAM Interrupt Controller Four Timers 20 Virtual 2 Virtual 32-Bit RISC Communications Processor (CP) and Program ROM SCC2 USB SPI Timer Non-Multiplexed Serial Interface MPC8xx Core Instruction IDMA Channels Serial DMA and Channels Unified Bus Communications Processor Module Peripheral Bus SCC3 I2C — UTOPIA Ports (850SAR) SMC1 SMC2 Time Slot Assigner TDMa |
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