3 Bit Constant Current LED Driver with PWM Control

A6280

8

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Dot Correction Control

The A6280 can further control the maximum output current for

each output by setting the three 7 bit dot correction registers with

scale data that ranges from 36.5% to 100% of the overall maxi-

is useful because not every type of LED (red, green, or blue, for

example) has the same level of brightness or intensity for any

given current, and the brightness could be different even from

LED to LED of the same type. By scaling the output currents so

that all the LEDs have matched intensities, the application will

have full color depth when using the PWM counters. The dot

correction current can be calculated by the following equation:

Refer to figure 6 for the bit configurations for the scalar registers.

The dot correction data in the shift registers is latched on a rising

edge of the Latch In (LI) pin. The latched dot correction data

remains latched on a rising OEI signal. The default output cur-

rent when the A6280 is powered up or recovers from a UVLO is

Package Power Dissipation

The maximum allowable package power dissipation is deter-

mined as:

The actual package power dissipation is:

When calculating power dissipation, the total number of avail-

able device outputs is usually used for the worst-case situation

(i.e., displaying all 3 LEDs at 100% DC).

Thermal Shutdown (TSD)

When the junction temperature of the A6280 reaches the thermal

outputs will shut off until the junction temperature cools down

shift registers and output latches will remain active during the

TSD event. Therefore there is no need to reset the data in the

output latches.

Undervoltage Lockout

The A6280 includes an internal undervoltage lockout (UVLO)

circuit that disables the driver outputs in the event of the logic

supply voltage dropping below a minimum acceptable level.

This prevents the display of erroneous information, a necessary

function for some critical applications. The shift registers will

not shift any data in a UVLO condition. Upon recovery of the

logic supply voltage and on power up, all internal shift registers

and latches will be set to zero.

Ballast Resistors

The voltage on the outputs should be kept in the range 1 to 3 V.

If the voltage goes below 1V, the current will begin to rolloff

dissipation may become a problem, as each output contributes

power supply nominal voltage is chosen to keep the output volt-

age in this range. Alternatively, series resistors can be added to

dissipate the extra power and keep the output voltage within the

recommended range.

Bits

0 1 2 3 4 5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

29 30

PWM Counter 0

PWM Counter 1

PWM Counter 2

0

Dot Correction

Register 0

Clock

Divider

0

Dot Correction

Register 1

000

Dot Correction

Register 2

0 ATB* ATB* 1

*Allegro Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application.

Figure 6. Register Configuration