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DS1345YF-70-IND Datasheet(PDF) 8 Page - Maxim Integrated Products |
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DS1345YF-70-IND Datasheet(HTML) 8 Page - Maxim Integrated Products |
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8 / 12 page  DS1345Y/AB 8 of 12 POWER-DOWN/POWER-UP TIMING (tA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Fail Detect to CE and WE Inactive tPD 1.5 µs 11 VCC slew from VTP to 0V tF 150 µs VCC Fail Detect to RST Active tRPD 15 µs 14 VCC slew from 0V to VTP tR 150 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms VCC Valid to RST Inactive tRPU 150 200 350 ms 14 VCC Valid to BW Valid tBPU 1 s 14 BATTERY WARNING TIMING (tA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Battery Test Cycle tBTC 24 hr Battery Test Pulse Width tBTPW 1 s Battery Test to BW Active tBW 1 s (tA = 25 °C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. |
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