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TLK6201EARGTR Datasheet(PDF) 3 Page - Texas Instruments |
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TLK6201EARGTR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 19 page www.ti.com DEVICE INFORMATION 1 2 3 4 GND DIN+ DIN– GND 12 11 10 9 16 VCC DOUT+ DOUT– VCC 15 14 13 5 6 7 8 P0019-04 EP RGTPACKAGE (TOP VIEW) TLK6201EA SLLS738 – AUGUST 2006 An on-chip band-gap voltage circuit generates a supply-voltage-independent reference from which all internally required voltages and bias currents are derived. The TLK6201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package, with a lead pitch of 0.5 mm. The pinout is shown in Figure 2. Figure 2. Pinout of TLK6201EA TERMINAL FUNCTIONS TERMINAL TYPE DESCRIPTION NAME NO. Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between COC0 16 Analog this pin and COC1 (pin 15). To disable the offset cancellation loop, connect COC1 and COC0 (pins 15 and 16). Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between COC1 15 Analog this pin and COC0 (pin 16). To disable the offset cancellation loop, connect COC1 and COC0 (pins 15 and 16). DE0 7 CMOS in Selects 4 dB of output signal de-emphasis when set to high level. Internally pulled up. DE1 6 CMOS in Selects 8 dB of output signal de-emphasis when set to high level. Internally pulled up. Noninverted data input. On-chip load terminated to ground. Connect a 100- Ω differential DIN+ 2 Analog in transmission line to terminals DIN+ and DIN–. Inverted data input. On-chip load terminated to ground. Connect a 100- Ω differential DIN– 3 Analog in transmission line to terminals DIN+ and DIN–. DIS 13 CMOS in Disables CML output stage when set to high level. Internally pulled down. DOUT+ 11 CML out Noninverted data output. On-chip 50- Ω back-terminated to VCC. DOUT– 10 CML out Inverted data output. On-chip 50- Ω back-terminated to VCC. GND 1, 4, EP Supply Circuit ground. Exposed die pad (EP) must be grounded. LOS 14 CMOS out High level indicates that the input signal amplitude is below the fixed threshold level. Output data signal polarity select (internally pulled up): Setting to high level or leaving pin POL 8 CMOS in open selects normal polarity. Low level selects inverted polarity. Output swing control. The output swing is increased by 50% when set to high level. SWG 5 CMOS in Internally pulled down. VCC 9, 12 Supply 3.3-V, ±10% supply voltage 3 Submit Documentation Feedback |
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