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AD8112 Datasheet(PDF) 6 Page - Analog Devices |
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AD8112 Datasheet(HTML) 6 Page - Analog Devices |
6 / 28 page AD8112 Rev. 0 | Page 6 of 28 TIMING CHARACTERISTICS (PARALLEL) Table 4. Limit Parameter Symbol Min Max Unit Data Setup Time t1 20 ns CLK Pulse Width t2 100 ns Data Hold Time t3 20 ns CLK Pulse Separation t4 100 ns CLK to UPDATE Delay t5 0 ns UPDATE Pulse Width t6 50 ns Propagation Delay, UPDATE to Switch On or Off 50 ns CLK, UPDATE Rise and Fall Times 100 ns RESET Time 200 ns t5 t6 t4 t2 t1 t3 1 0 1 0 1= LATCHED CLK D0 TO D4 A0 TO A2 0 = TRANSPARENT UPDATE Figure 3. Timing Diagram, Parallel Mode Table 5. Logic Levels Pins VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE 2.0 V min 0.8 V max 20 μA max −400 μA min DATA OUT 2.7 V min 0.5 V max −400 μA max 3.0 mA min |
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