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M41T93RMY6E Datasheet(PDF) 10 Page - STMicroelectronics |
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M41T93RMY6E Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 49 page  Summary description M41T93 10/49 Figure 5. Hardware hookup 1. Open drain output 2. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU. 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ. Figure 6. Data and clock timing AI11822 VCC Reset Input (ST6, ST7, ST9, ST10, Others) SCL (2) SPI Interface with (CPOL, CPHA) = (0,0) or (1,1) SDI SDO CS 32kHz CLKIN XO XI M41T93 MCU VSS VBAT IRQ/FT/OUT (1) RST (1) SDI SQW SDO SCL VCC INT E VCC Table 2. Function table Mode E SCL SDI SDO Disable Reset H Input Disabled Input disabled High Z WRITE L Data bit latch High Z READ L X Next data bit shift (1) AI04630 AI04631 AI04632 C C MSB LSB CPHA SDI 0 1 CPOL 0 1 MSB LSB SDO |
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