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SST25LF020A Datasheet(PDF) 8 Page - Silicon Storage Technology, Inc

Part # SST25LF020A
Description  2 Mbit / 4 Mbit SPI Serial Flash
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST25LF020A Datasheet(HTML) 8 Page - Silicon Storage Technology, Inc

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Data Sheet
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
©2006 Silicon Storage Technology, Inc.
S71242-05-000
1/06
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25LF020A/040A. The instruction
bus cycles are 8 bits each for commands (Op Code), data,
and addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
TABLE
6: DEVICE OPERATION INSTRUCTIONS1
1. AMS = Most Significant Address
AMS = A17 for SST25LF020A and A18 for SST25LF040A
Address bits above the most significant bit of each density can be VIL or VIH
Cycle Type/
Operation2,3
2. Operation: SIN = Serial In, SOUT = Serial Out
3. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
Max
Freq
MHz
Bus Cycle4
4. One bus cycle is eight clock periods.
12
3
4
5
6
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT
Read
20
03H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
X
DOUT
High-Speed-Read
33
0BH
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
X
X
X
DOUT
Sector-Erase5,6
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
must be executed.
20H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
-
-
Block-Erase5,7
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
52H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
-
-
Chip-Erase6
60H
Hi-Z
-
-----
-
-
Byte-Program6
02H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
Auto Address Increment
(AAI) Single-Byte Program6,8
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
AFH
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
Read-Status-Register
(RDSR)
05H
Hi-Z
X
DOUT
-Note9
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
-Note9
-Note9
Enable-Write-Status-Register
(EWSR)10
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
50H
Hi-Z
-
-----
-
-
Write-Status-Register
(WRSR)10
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
Write-Enable (WREN)
06H
Hi-Z
-
-----
-
-
Write-Disable (WRDI)
04H
Hi-Z
-
-----
-
-
Read-ID
90H or
ABH
Hi-Z
00H
Hi-Z
00H
Hi-Z
ID
Addr11
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer and Device
ID output stream is continuous until terminated by a low to high transition on CE#
Hi-Z
X
DOUT12
12. Device ID = 43H for SST25LF020A and 44H for SST25LF040A
T6.0 1242


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