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MAX708SEPA Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX708SEPA Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 15 page +3V Voltage Monitoring, Low-Cost µP Supervisory Circuits _______________________________________________________________________________________ 7 RESET and RESET Outputs A microprocessor’s (µP’s) reset input starts in a known state. When the µP is in an unknown state, it should be held in reset. The MAX706P/R/S/T and the MAX706AP/ AR/AS/AT assert reset when VCC is low, preventing code execution errors during power-up, power-down, or brownout conditions. On power-up once VCC reaches 1V, RESET is guaran- teed to be logic-low and RESET is guaranteed to be logic-high. As VCC rises, RESET and RESET remain asserted. Once VCC exceeds the reset threshold, the internal timer causes RESET and RESET to be deasserted after a time equal to the reset pulse width, which is typically 200ms (Figure 3). If a power-fail or brownout condition occurs (i.e., VCC drops below the reset threshold), RESET and RESET are asserted. As long as VCC remains below the reset threshold, the internal timer is continually reset, causing the RESET and RESET outputs to remain asserted. Thus, a brownout condition that interrupts a previously initiated reset pulse causes an additional 200ms delay from the time the latest interruption occurred. On power-down once VCC drops below the reset threshold, RESET and RESET are guaranteed to be asserted for VCC ≥ 1V. The MAX706P/MAX706AP provide a RESET signal, and the MAX706R/S/T and MAX706AR/AS/AT provide a RESET signal. The MAX708R/S/T provide both RESET and RESET. Watchdog Timer The MAX706P/R/S/T and the MAX706AP/AR/AS/AT watchdog circuit monitor the µP’s activity. If the µP does not toggle the watchdog input (WDI) within 1.6s, the watchdog output (WDO) goes low (Figure 4). If the reset signal is asserted, the watchdog timer will be reset to zero and disabled. As soon as reset is released, the timer starts counting. WDI can detect puls- es as narrow as 100ns with a 2.7V supply and 50ns with a 4.5V supply. The watchdog timer for the MAX706P/R/S/T cannot be disabled. The watchdog timer for the MAX706AP/AR/AS/AT operates similarly to the MAX706P/R/S/T. However, the watchdog timer for the MAX706AP/AR/AS/AT disables when the WDI input is left open or connected to a tri-state output in its high- impedance state and with a leakage current of less than 600nA. The watchdog timer can be disabled any- time, provided WDO is not asserted. RESET GENERATOR VCC 70µA 8 7 RESET RESET 5 PFO GND 3 1.25V 2.63V MAX708R 2.93V MAX708S 3.08V MAX708T 1 MR 2 VCC 4 PFI MAX708R/S/T Figure 1. MAX706_ Functional Diagram Figure 2. MAX708_ Functional Diagram WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER TIMEBASE FOR RESET AND WATCHDOG RESET GENERATOR VCC 70µA 8 WDO 7 RESET (RESET) 5 PFO GND 3 1.25V 2.63V MAX706P/R 2.93V MAX706S 3.08V MAX706T ( ) ARE FOR MAX706P/AP. 6 WDI 1 MR 2 VCC 4 PFI MAX706P/R/S/T MAX706AP/AR/AS/AT |
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