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MC9328MX21VK Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC9328MX21VK Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 98 page  MC9328MX21 Technical Data, Rev. 3.1 10 Freescale Semiconductor Signal Descriptions PC_POE PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is multiplexed with NFCLE signal of NF. PC_RW PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read access and negated low for write access. This signal is multiplexed with NFRE signal of NF. PC_PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized. CSPI CSPI1_MOSI Master Out/Slave In signal CSPI1_MISO Master In/Slave Out signal CSPI1_SS[2:0] Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and CSPI1_SS1 is multiplexed with EXT_DMAGRANT. CSPI1_SCLK Serial Clock signal CSPI1_RDY Serial Data Ready signal. Also multiplexed with EXT_DMAREQ. CSPI2_MOSI Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG. CSPI2_MISO Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG. CSPI2_SS[2:0] Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS, USBH2_RXDP and USBH2_RXDM signal of USB OTG CSPI2_SCLK Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG CSPI3_MOSI Master Out/Slave In signal. This signal is multiplexed with SD1_CMD. CSPI3_MISO Master In/Slave Out signal. This signal is multiplexed with SD1_D0. CSPI3_SS Slave Select (Selectable polarity) signal multiplexed with SD1_D3. CSPI3_SCLK Serial Clock signal. This signal is multiplexed with SD1_CLK. General Purpose Timers TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and Reset Controller module. TOUT1 (or simply TOUT) Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1 and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT. TOUT2 Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO. TOUT3 Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO. USB On-The-Go USB_BYP USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO. USB_PWR USB Power output signal USB_OC USB Over current input signal. This signal can only be used for USB function, not for GPIO. USBG_RXDP USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15. USBG_RXDM USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14. USBG_TXDP USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13. USBG_TXDM USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12. USBG_RXDAT USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2. Table 2. i.MX21 Signal Descriptions (Continued) Signal Name Function/Notes |
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Similar Description - MC9328MX21VK |
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