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SST25VF040-20-4E-QAE Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc

Part # SST25VF040-20-4E-QAE
Description  2 Mbit / 4 Mbit SPI Serial Flash
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST25VF040-20-4E-QAE Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc

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10
EOL Product Data Sheet
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF040
©2006 Silicon Storage Technology, Inc.
S71231(04)-00-000
10/06
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total program-
ming time when the entire memory array is to be pro-
grammed. An AAI program instruction pointing to a
protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when ini-
tiating an AAI program instruction.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI program instruction
is initiated by executing an 8-bit command, AFH, followed
by address bits [A23-A0]. Following the addresses, the data
is input sequentially from MSB (bit 7) to LSB (bit 0). CE#
must be driven high before the AAI program instruction is
executed. The user must poll the BUSY bit in the software
status register or wait TBP for the completion of each inter-
nal self-timed Byte-Program cycle. Once the device com-
pletes programming byte, the next sequential address may
be program, enter the 8-bit command, AFH, followed by the
data to be programmed. When the last desired byte had
been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to
ensure the device completes programming. See Figure 7
for AAI programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0).
FIGURE 7: Auto Address Increment (AAI) Program Sequence
CE#
SI
SCK
A[23:16] A[15:8]
A[7:0]
AF
Data Byte 1
AF
Data Byte 2
CE#
SI
SO
SCK
Write Disable (WRDI)
Instruction to terminate
AAI Operation
Read Status Register (RDSR)
Instruction to verify end of
AAI Operation
04
Last Data Byte
AF
05
DOUT
MODE 3
MODE 0
TBP
TBP
TBP
1231 F06.1
0 1 2 3 4 5 6 7 8
3233343536373839
15 16
23 24
31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
01
01234567
0123456789 10 11 12 13 14 15
0123456789 10 11 12 13 14 15


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