ZL30108

Data Sheet

9

Zarlink Semiconductor Inc.

Exceeding the threshold of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle

and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the

reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency

failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less

than 2.5 s each have an accumulative effect and will disqualify the reference. This is illustrated in Figure 4.

Figure 4 - Behavior of the Dis/Requalify Timer

When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output

signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL

status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode

(Holdover/Normal) of the DPLL.

Figure 5 - Out-of-Range Thresholds for OOR_SEL=1

2.5 s

10 s

current REF

timer

REF_FAIL

SCM or CFM failure

HOLDOVER

C20i Clock Accuracy

0 ppm

+32 ppm

-32 ppm

0

51

83

64

32

32

-32

-96

-75

-50

0

-25

25

75

Frequency offset [ppm]

Out of Range

Out of Range

Out of Range

In Range

In Range

In Range

C20

50

-64

-83

115

96

-32

-51

-115

C20

C20

100

-100