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SST34HF164G-70-4E-L3KE Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc

Part # SST34HF164G-70-4E-L3KE
Description  16 Mbit Dual-Bank Flash 2/4 Mbit SRAM ComboMemory
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST34HF164G-70-4E-L3KE Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc

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Preliminary Specifications
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
5
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
Product Identification
The Product Identification mode identifies the device as
SST34HF162G or SST34HF164G and the manufacturer
as SST. This mode may be accessed by software opera-
tions only. The hardware device ID Read operation, which
is typically used by programmers cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users may
use the software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple man-
ufacturers in the same socket. For details, see Tables 4 and
5 for software operation, Figure 15 for the Software ID
Entry and Read timing diagram and Figure 23 for the ID
Entry command sequence flowchart.
Note: BK = Bank Address (A19-A18)
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for software command codes, Fig-
ure 16 for timing waveform and Figure 23 for a flowchart.
SRAM Operation
With BES# low and BEF# high, the SST34HF162G/164G
operate as either 128K x16 or 256K x16 CMOS SRAM,
with fully static operation requiring no external clocks or
timing strobes. The SST34HF162G/164G SRAM is
mapped into the first 128 KWord address space. When
BES# and BEF# are high, all memory banks are dese-
lected and the device enters standby. Read and Write
cycle times are equal. The control signals UBS# and LBS#
provide access to the upper data byte and lower data byte.
See Table 4 for SRAM Read and Write data byte control
modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162G/164G is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram, Figure 4, for fur-
ther details.
SRAM Write
The SRAM Write operation of the SST34HF162G/164G is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE# whichever occurs first. The
write time is measured from the last falling edge of BES#
or WE# to the first rising edge of BES# or WE#. Refer to
the Write cycle timing diagrams, Figures 5 and 6, for fur-
ther details.
TABLE
2: PRODUCT IDENTIFICATION
ADDRESS
DATA
Manufacturer’s ID
BK0000H
00BFH
Device ID
SST34HF16xG
BK0001H
734BH
T2.0 1276


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