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SST32HF1642C-70-4E-LFSE Datasheet(PDF) 6 Page - Silicon Storage Technology, Inc |
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SST32HF1642C-70-4E-LFSE Datasheet(HTML) 6 Page - Silicon Storage Technology, Inc |
6 / 36 page 6 Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282 SST32HF1622C / SST32HF1642C / SST32HF3242C ©2005 Silicon Storage Technology, Inc. S71253-03-000 5/05 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 6 for software command codes, Figure 15 for timing waveform and Figure 23 for a flowchart. Security ID The SST32HFx2/x2C devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit seg- ments - one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment is left un-programmed for the customer to pro- gram as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three- byte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. I/O Buffers 1253 B1.1 Address Buffers DQ15 - DQ8 AMS-A0 WE 1# SuperFlash Memory SRAM/ PSRAM Control Logic BES1# BES2 BEF# OE 1# RESET# WP# Address Buffers & Latches LBS# UBS# DQ7 - DQ0 Notes: 1. For LS package only: WE# = WEF# and/or WES# OE# = OEF# and/or OES# FUNCTIONAL BLOCK DIAGRAM |
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