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ZL30123GGG2 Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc |
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ZL30123GGG2 Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc |
9 / 27 page ZL30123 Data Sheet 9 Zarlink Semiconductor Inc. Master Clock K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous B5 NC No Connection. Leave unconnected. C5 IC No Connection. Leave unconnected. D1 IC No Connection. Leave unconnected. J2 IC Internal Connection. Connect to ground. J6 IC Internal Connection. Connect to ground. G3 IC No Connection. Leave unconnected. K6 IC Internal Connection. Leave unconnected. F2 IC Internal Connection. Leave unconnected. F3 IC Internal Connection. Leave unconnected. H7 IC Internal Connection. Connect to ground. Power and Ground D9 E4 G8 G9 J8 J9 H6 H8 VDD P P P P P P P P Positive Supply Voltage. +3.3VDC nominal. E8 F4 VCORE P P Positive Supply Voltage. +1.8VDC nominal. A5 A8 C10 AVDD P P P Positive Analog Supply Voltage. +3.3VDC nominal. B7 B8 H2 AVCORE P P P Positive Analog Supply Voltage. +1.8VDC nominal. Pin # Name I/O Type Description |
Similar Part No. - ZL30123GGG2 |
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Similar Description - ZL30123GGG2 |
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