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SST34HF3284-70-4E-LSE Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST34HF3284-70-4E-LSE Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 41 page  2 Data Sheet 32 Mbit Concurrent SuperFlash + 4/8 Mbit PSRAM ComboMemory SST34HF3244 / SST34HF3282 / SST34HF3284 ©2006 Silicon Storage Technology, Inc. S71335-00-000 8/06 completion of Program operation. To protect against inad- vertent flash write, the SST34HF32xx devices contain on- chip hardware and software data protection schemes. The flash and PSRAM operate as two independent mem- ory banks with respective bank enable signals. The mem- ory bank selection is done by two bank enable signals. The PSRAM bank enable signals, BES1# and BES2, select the PSRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Pro- gram operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. Designed, manufactured, and tested for applications requir- ing low power and small form factor, the SST34HF32xx are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figures 2 and 3 for pin assignments. Device Operation The SST34HF32xx uses BES1#, BES2 and BEF# to con- trol operation of either the flash or the PSRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the PSRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and PSRAM memory banks which minimizes power consump- tion and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. Concurrent Read/Write Operation Dual bank architecture of SST34HF32xx devices allows the Concurrent Read/Write operation whereby the user can read from one bank while programming or erasing in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Table 3 for dual-bank memory organization. Note: For the purposes of this table, write means to perform Block-/Sector-Erase or Program operations as applicable to the appropriate bank. Flash Read Operation The Read operation of the SST34HF32xx is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to Figure 7, the Read cycle timing diagram, for further details. CONCURRENT READ/WRITE STATES Flash PSRAM Bank 1 Bank 2 Read Write No Operation Write Read No Operation Write No Operation Read No Operation Write Read Write No Operation Write No Operation Write Write |
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