TAS5015

SLES017 – SEPTEMBER 2001

5

www.ti.com

functional description

serial audio port

The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin),

and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1-kHz, 48-kHz,

88.2-kHz, 96-kHz, 176.4-kHz, or 192-kHz stereo). See the serial interface formats section.

system clocks—master mode and slave mode

The TAS5015 allows multiple system clocking schemes. Master mode indicates that the TAS5015 provides

system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 128 Fs MCLK_OUT

(quad speed), 64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode.

Slave mode indicates that a system master other than the TAS5015 provides system clocks (LRCLK, SCLK,

and MCLK_IN) to the TAS5015 (M_S = 0). The TAS5015 operates with LRCLK and SCLK synchronized to

MCLK. The TAS5015 does not require any specific phase relationship between LRCLK and MCLK, but there

must be synchronization. In the slave mode, MCLK_OUT is driven low. Table 1 shows all the possible master

and slave modes.

sampling frequency

The normal sampling frequency is either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the

normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or

Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either

22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection.

Table 1. External Clock and External PLL Functions

DESCRIPTION

M_S

DBSPD

DEM_EN

DEM_SEL

MCLK_IN

(MHz)

HFCLK

(MHz)

SCLK

(MHz)

LRCLK

(KHz)

MCLK_OUT

(MHz)

External PLL, master, normal

1

0

0

0

90 3168

2 8224

44 1

11 2896

External PLL, master, normal

speed (see Notes 1 and 2)

1

0

1

0

–

90.3168

2.8224

44.1

11.2896

External PLL, master, normal

1

0

1

1

98 304

3 072

48

12 288

External PLL, master, normal

speed (see Notes 1 and 2)

1

0

0

0

–

98.304

3.072

48

12.288

External PLL, master, double

speed (see Notes 1 and 2)

1

1

0

0

–

90.3168

5.6448

88.2

22.5792

External PLL, master, double

speed (see Note 1 and 2)

1

1

0

0

–

98.304

6.144

96

24.576

External PLL, master, quad speed

(see Notes 1 and 2)

1

0

0

1

–

90.3168

11.2896

176.4

22.5792

External PLL, master, quad speed

(see Notes 1 and 2)

1

0

0

1

–

98.304

12.288

192

24.576

External PLL, slave, normal speed

0

0

0

0

11 2896

90 3168

2 8224

44 1

11 2896

External PLL, slave, normal s eed

(see Notes 3, 4, and 5)

0

0

1

0

11.2896

90.3168

2.8224

44.1

11.2896

External PLL, slave, normal speed

0

0

1

1

12 288

98 304

3 072

48

12 288

External PLL, slave, normal s eed

(see Notes 3, 4, and 5)

0

0

0

0

12.288

98.304

3.072

48

12.288

NOTES:

1. SCLK and LRCLK are outputs

2. MCLK_IN tied LOW

3. External MCLK connected to MCLK_IN input

4. SCLK and LRCLK are inputs

5. MCLK_OUT is a buffered version of the external MCLK input