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ZL30406 Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL30406 Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
10 / 21 page ZL30406 Data Sheet 10 Zarlink Semiconductor Inc. 2.2.3 CML to LVDS Interface To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the VCM (common mode voltage) as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for LVDS applications. Figure 8 - LVDS Termination 2.2.4 CML to LVPECL Interface In the case when more than four 77.76 MHz clocks are required to drive LVPECL receivers then the unused OC- CLKo clock (CML output) can be configured to output the 77.76 MHz clock and interface to the LVPECL receiver as is shown in the Figure 9. The terminating resistors should be placed as close as possible to the LVPECL receiver. Figure 9 - CML to LVPECL Interface ZL30406 CML Z=50 Ω Z=50 Ω Driver 0.1 uF +3.3 V GND VCC LVDS 10 nF 10 nF Receiver R1 R2 VCC=+3.3 V R1 R2 100 Ω Typical resistor values: R1 = 16 k Ω, R2 = 10 kΩ OC-CLKoP OC-CLKoN LVPECL CML ZL30406 Z=50 Ω Z=50 Ω Receiver GND Typical resistor values: R1 = 82 Ω, R2 =130 Ω R1 R2 VCC=+3.3 V R1 R2 VCC 0.1 uF +3.3 V Driver 10 nF 10 nF OC-CLKoP OC-CLKoN 77.76MHz |
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