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TAS5152 Datasheet(PDF) 2 Page - Texas Instruments |
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TAS5152 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 26 page TAS5152 SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005 www.ti.com 2 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION The TAS5152 is available in a 36-pin PSOP3 (DKD) thermally enhanced package. The package contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GVDD_B OTW SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D VDD GVDD_C GVDD_A BST_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D BST_D GVDD_D DKD PACKAGE (TOP VIEW) MODE Selection Pins MODE PINS PWM INPUT OUTPUT CONFIGU- PROTECTION SCHEME M3 M2 M1 CONFIGU- RATION SCHEME 0 0 0 2N (1) AD/BD modulation 2 channels BTL output BTL mode (2) 0 0 1 Reserved 0 1 0 1N (1) AD modulation 2 channels BTL output BTL mode (2) 0 1 1 1N (1) AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used. 1 0 0 1N (1) AD modulation 4 channels SE output Protection works similarly to BTL mode (2). Only difference in SE mode is that OUT_x is Hi-Z instead of a pulldown through internal pulldown resistor. 1 0 1 1 1 0 Reserved 1 1 1 Reserved (1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. (2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP) and power-on reset (POR) affect all channels. Package Heat Dissipation Ratings (1) PARAMETER TAS5152DKD RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors) 1.28 RθJC 〈°C/W)—1 BTL or 2 SE channel(s) (4 transistors) 2.56 RθJC (°C/W)—(1 transistor) 8.6 Pad area (2) 80 mm2 (1) JC is junction-to-case, CH is case-to-heatsink. (2) RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RθCH with this condition is 0.8°C/W for the DKD package and 1.8 °C/W for the DDV package. |
Similar Part No. - TAS5152_07 |
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Similar Description - TAS5152_07 |
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