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TAS5186ADDVRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS5186ADDVRG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 18 page  www.ti.com THEORY OF OPERATION POWER SUPPLIES SYSTEM POWER-UP/DOWN SEQUENCE Powering Down Error Reporting TAS5186A SLES156 – OCTOBER 2005 reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same To facilitate system design, the TAS5186A needs side of the PCB as the TAS5186A. It is only a 12-V supply in addition to a typical 39-V recommended to follow the PCB layout of the power-stage supply. An internal voltage regulator TAS5186A reference design. For additional provides suitable voltage levels for the digital and information on the recommended power supply and low-voltage analog circuitry. Additionally, all circuitry required components, see the application diagrams requiring a floating voltage supply, e.g., the high-side given in this data sheet. The 12-V supply should be gate drive, is accommodated by built-in bootstrap powered from a low-noise, low-output-impedance circuitry requiring only a few external capacitors. voltage regulator. Likewise, the 39-V power-stage supply is assumed to have low output impedance and In order to provide outstanding electrical and acoustic low noise. The power-supply sequence is not critical characteristics, the PWM signal path including gate due to the internal power-on-reset circuit. Moreover, drive and output stage is designed as identical, the TAS5186A is fully protected against erroneous independent half-bridges. For this reason, each power-stage turnon due to parasitic gate charging. half-bridge has separate bootstrap pins (BST_X) and Thus, voltage-supply ramp rates (dv/dt) are typically power-stage supply pins (PVDD_X). Furthermore, an noncritical. additional pin (VDD) is provided as power supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_X and VDD on the printed-circuit board (PCB) The TAS5186A does not require a power-up by RC filters (see application diagram for details). sequence. The outputs of the H-bridge remain in a These RC filters provide the recommended high-impedance state until the gate-drive supply high-frequency isolation. Special attention should be voltage (GVDD_X) and VDD voltage are above the paid to placing all decoupling capacitors as close to undervoltage protection (UVP) voltage threshold (see their associated pins as possible. In general, the Electrical Characteristics section of this data inductance between the power-supply pins and sheet). Although not specifically required, it is decoupling capacitors must be avoided. (See recommended to hold RESET in a low state while reference board documentation for additional powering up the device. information.) When the TAS5186A is being used with TI PWM For a properly functioning bootstrap circuit, a small modulators such as the TAS5086, no special ceramic capacitor must be connected from each attention to the state of RESET is required, provided bootstrap pin (BST_X) to the power-stage output pin that the chipset is configured as recommended. (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. The TAS5186A does not require a power-down When the power-stage output voltage is high, the sequence. The device remains fully operational as bootstrap capacitor voltage is shifted above the long as the gate-drive supply (GVDD_X) voltage and output voltage potential and thus provides a suitable VDD voltage are above the undervoltage protection voltage supply for the high-side gate driver. In an (UVP) threshold level (see the Electrical application with PWM switching frequencies in the Characteristics section of this data sheet). Although range 352 kHz to 384 kHz, it is recommended to use not specifically required, it is a good practice to hold 33-nF ceramic capacitors, size 0603 or 0805, for the RESET low during power down, thus preventing bootstrap capacitor. These 33-nF capacitors ensure audible artifacts including pops and clicks sufficient energy storage, even during minimal PWM When the TAS5186A is being used with TI PWM duty cycles, to keep the high-side power stage FET modulators such as the TAS5086, no special (LDMOS) fully started during all of the remaining part attention to the state of RESET is required, provided of the PWM cycle. In an application running at a that the chipset is configured as recommended. reduced switching frequency, generally 250 kHz to 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes The SD and OTW pins are both active-low, component selection, PCB placement and routing. As open-drain outputs. Their function is for indicated, each half-bridge has independent protection-mode signaling to a PWM controller or power-stage supply pins (PVDD_X). For optimal other system-control device. electrical performance, EMI compliance, and system 11 |
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