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ZL50010GDC Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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ZL50010GDC Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
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1 / 87 page  1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. Features • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop (DPLL) meets Telcordia GR-1244-CORE Stratum 4 enhanced specifications • DPLL provides automatic reference switching, jitter attenuation, holdover and free run functions • Per-stream ST-BUS input with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps • Per-stream ST-BUS output with data rate selection of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps; the output data rate can be different than the input data rate • Per-stream high impedance control output for every ST-BUS output with fractional bit advancement • Per-stream input channel and input bit delay programming with fractional bit delay • Per-stream output channel and output bit delay programming with fractional bit advancement • Multiple frame pulse outputs and reference clock outputs • Per-channel constant throughput delay • Per-channel high impedance output control • Per-channel message mode • Per-channel Pseudo Random Bit Sequence (PRBS) pattern generation and bit error detection • Control interface compatible to Motorola non- multiplexed CPUs • Connection memory block programming capability • IEEE-1149.1 (JTAG) test port • 3.3 V I/O with 5 V tolerant input April 2006 Ordering Information ZL50010/QCC 160 Pin LQFP Trays ZL50010/GDC 144 Ball LBGA Trays ZL50010QCG1 160 Pin LQFP* Trays, Bake & Drypack ZL50010GDG2 144 Ball LBGA** Trays, Bake & Drypack *Pb Free Matte Tin **Pb Free Tin/Silver/Coppoer -40 °C to +85°C ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Figure 1 - ZL50010 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Test Port Microprocessor Interface VSS VDD STo0-15 RESET Connection Memory CKo1 STi0-15 APLL FPo1 ODE Input Timing Data Memory S/P Converter P/S Converter Output HiZ Control STOHZ0-15 CKo0 FPo0 CKo2 FPo2 CKi FPi OSC DPLL PRI_REF and Internal Registers Output Timing CLKBYPS IC0 - 4 SEC_REF |
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