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ZL50012GDC Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL50012GDC Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 66 page  ZL50012 Data Sheet 13 Zarlink Semiconductor Inc. 11 B9 SG1 APLL Test Control (3.3 V Input with internal pull-down): For normal operation, this input MUST be low. 12 A9 TM1 APLL Test Pin 1: For normal operation, this input MUST be low. 13 C10 TM2 APLL Test Pin 2: For normal operation, this input MUST be low. 14, 15, 19 C9, C8, A8 NC1, NC2, NC3 No Connection: These pins MUST be left unconnected. 16 D8 Vss_APLL Ground for the APLL Circuit. 17 B8 VDD_APLL Power Supply for the on-chip Analog Phase Lock Loop (APLL) Circuit: +3.3 V 20 A7 ICONN1 Internal Connection: In normal mode, this pin must be low. 22 B7 CLKBYPS Test Clock Input: For device testing only, in normal operation, this input MUST be low. 24 - 28 A6, A5, B6, B5, C7 IC0 - 4 Internal connection (3.3 V Tolerant Inputs with internal pull-down): In normal mode, these pins must be low. 30, 31 C4, A4 ICONN2 - 3 Internal Connection: In normal mode, these pins must be low. 34 A3 FPo0 ST-BUS Frame Pulse Output 0 (5 V Tolerance Three-state Output): ST-BUS frame pulse output which stays low for 244 ns or 122 ns at the output frame boundary. Its frequency is 8 KHz. The polarity of this signal can be changed using the Internal Mode Selection register. 35 B4 CKo0 ST-BUS Clock Output 0 (5 V Tolerant Three-state Output): A 4.094 MHz or 8.192 MHz clock output. The clock falling edge defines the output frame boundary. The polarity of this signal can be changed using the Internal Mode Selection register. 36 B3 FPo1 ST-BUS Frame Pulse Output 1 (5 V Tolerant Three-state Output): ST-BUS frame pulse output which stays low for 61 ns or 122 ns at the output frame boundary. Its frequency is 8 KHz. The polarity of this signal can be changed using the Internal Mode Selection register. 37 B2 CKo1 ST-BUS Clock Output 1 (5 V Tolerant Three-state Output): A 16.384 MHz or 8.192 MHz clock output. The clock falling edge defines the output frame boundary. The polarity of this signal can be changed using the Internal Mode Selection register. Pin Description (continued) LQFP Pin Number LBGA Ball Number Name Description |
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