ZL49010/11, ZL49020/21, ZL49030/31

Data Sheet

5

Zarlink Semiconductor Inc.

of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit

binary representing all 16 standard DTMF digits are shown in Table 2.

Powerdown Mode (ZL4901x/4903x)

The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in

use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be

kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).

Table 3 - Powerdown Mode

DIGIT

697

1209

1

0

0

0

1

697

1336

2

0

0

1

0

697

1477

3

0

0

1

1

770

1209

4

0

1

0

0

770

1336

5

0

1

0

1

770

1477

6

0

1

1

0

852

1209

7

0

1

1

1

852

1336

8

1

0

0

0

852

1477

9

1

0

0

1

941

1336

0

1

0

1

0

941

1209

*

1

0

1

1

941

1477

#

1

1

0

0

697

1633

A

1

1

0

1

770

1633

B

1

1

1

0

852

1633

C

1

1

1

1

941

1633

D

0

0

0

0

0= LOGIC LOW, 1= LOGIC HIGH

Note: b0=LSB of decoded DTMF digit and shifted out first.

Table 2 - Serial Decode Bit Table

ACK (input)

PWDN (input)

ESt/DStD (output)

SD (output)

ZL4901x/4903x

status

low

low

Refer to Fig. 4 for

timing waveforms

Refer to Fig. 4 for

timing waveforms

normal operation

low

low

low

powerdown mode

high

low

low

undefined

undefined

high

high

undefined

undefined

undefined