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TAS5504A Datasheet(PDF) 8 Page - Texas Instruments |
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TAS5504A Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 97 page  www.ti.com TAS5504A 4-Channel Digital Audio PWM Processor SLES169 – FEBRUARY 2006 List of Tables 1-1 I2C Register 0xD0 Bit 30 Usage ................................................................................................. 14 1-2 Serial Data Formats .............................................................................................................. 18 1-3 TAS5504A Audio-Processing Feature Sets ................................................................................... 20 1-4 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) ...................................................... 27 1-5 Bass and Treble Filter Selections ............................................................................................... 28 1-6 Linear Gain Step Size ............................................................................................................ 28 1-7 Default Loudness Compensation Parameters ................................................................................. 30 1-8 Example Loudness Function Parameters ...................................................................................... 31 1-9 DRC Recommended Changes From TAS5504A Defaultss ................................................................. 32 2-1 Device Outputs During Reset ................................................................................................... 42 2-2 Values Set During Reset ......................................................................................................... 42 2-3 Device Outputs During Power Down ........................................................................................... 43 2-4 Device Outputs During Back-End Error ........................................................................................ 44 2-5 Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C) .......................................... 45 2-6 Recommended TAS5504A Configurations for Texas Instruments Power Stages ....................................... 46 2-7 Audio System Configuration (General Control Register 0xE0) .............................................................. 46 2-8 Volume Ramp Rates in ms ...................................................................................................... 47 6-1 Clock Control Register ........................................................................................................... 69 6-2 General Status Register (0x01) ................................................................................................. 69 6-3 System Control Register 1 ....................................................................................................... 70 6-4 System Control Register 2 ....................................................................................................... 70 6-5 Channel Configuration Control Registers ...................................................................................... 71 6-6 Headphone Configuration Control Register ................................................................................... 71 6-7 Serial Data Interface Control Register Format ................................................................................ 72 6-8 Soft-Mute Register (0x0F) ....................................................................................................... 72 6-9 Automute Control Register (0x14) .............................................................................................. 73 6-10 Automute PWM Threshold and Back-End Reset Period ..................................................................... 74 6-11 Modulation Index Limit Register ................................................................................................. 75 6-12 Bank Switching Command ....................................................................................................... 76 6-13 Input Mixer Registers Format (Channels 1–4) ................................................................................ 77 6-14 Bass Management Registers Format (0x49–0x50) ........................................................................... 78 6-15 Biquad Filters Register Format (0x51–0x88) .................................................................................. 79 6-16 Contents of One 20-Byte Biquad Filter Register Format (Default = All-Pass) ............................................ 79 6-17 Bass and Treble Bypass Register Format (0x89–0x90) ..................................................................... 79 6-18 Loudness Registers Format (0x91–0x95) ...................................................................................... 80 6-19 DCR1 Control (0x96, Channels 1–3) ........................................................................................... 80 6-20 DRC2 Control (0x97, Channel 4) ............................................................................................... 81 6-21 DRC1 Data Registers ............................................................................................................ 81 6-22 DRC2 Data Registers ............................................................................................................ 82 8 List of Tables |
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