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SST49LF020A-33-4C-WHE Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST49LF020A-33-4C-WHE Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
10 / 50 page 10 Data Sheet 2 Mbit LPC Flash SST49LF020A ©2006 Silicon Storage Technology, Inc. S71206-08-000 5/06 DESIGN CONSIDERATIONS SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket. PRODUCT IDENTIFICATION The Product Identification mode identifies the device as the SST49LF020A and manufacturer as SST. MODE SELECTION The SST49LF020A flash memory devices can operate in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The mode pin is used to set the interface mode selection. If the mode pin is set to logic High, the device is in PP mode. If the mode pin is set Low, the device is in the LPC mode. The mode selection pin must be configured prior to device operation. The mode pin is inter- nally pulled down if the pin is left unconnected. In LPC mode, the device is configured to its host using standard LPC interface protocol. Communication between Host and the SST49LF020A occurs via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the device is programmed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the lower internal addresses (A10-0), and the column addresses are mapped to the higher internal addresses (AMS-11). See Figure 4, the Device Memory Map, for address assignments. LPC MODE Device Operation The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a control line, LFRAME#, to control operations of the SST49LF020A. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specifi- cation, Revision 1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are incorporated into the standard LPC mem- ory cycles. See Figures 7 through 12 for command sequences. LPC signals are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular sequence, depending on whether they are Read or Write operations. LPC memory Read and Write cycle is defined in Tables 5 and 6. Both LPC Read and Write operations start in a similar way as shown in Figures 5 and 6. The host (which is the term used here to describe the device driving the memory) asserts LFRAME# for one or more clocks and drives a start value on the LAD[3:0] bus. At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be asserted one cycle before the start cycle to select the SST49LF020A for Read and Write operations. Once the SST49LF020A identify the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles. The LPC protocol supports a 32-bit address phase. The SST49LF020A encode ID and register space access in the address field. See Table 3 for address bits definition. For Write operation the Data cycle will follow the Address cycle, and for Read operation TAR and SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of the bus must be returned to the host by a 2-clock TAR cycle. TABLE 2: Product Identification Address Data Manufacturer’s ID 0000H BFH Device ID SST49LF020A 0001H 52H T2.2 1206 TABLE 3: Address bits definition A31: A23 A22 A21: A18 A17:A0 1111 1111 1b 1 = Memory Access 0 = Register access ID[3:0]1 1. See Table 7 for multiple device selection configuration. Device Memory address T3.0 1206 |
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