Rev.3.00, Jul.15.2005, page 1 of 7

HD74LS165A

Parallel-Load 8-bit Shift Register

REJ03D0449–0300

Rev.3.00

Jul.15.2005

access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /

load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs

are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit

function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift /

load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the

clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are

loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the

clock, clock inhibit, or serial inputs.

Features

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LS165AP

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

P

—

HD74LS165AFPEL

SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

EL (2,000 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Pin Arrangement

(Top view)

GND

15

16

1

2

3

4

5

6

7

14

8

9

10

11

12

13

Shift/

Load

Clock

E

F

G

H

Output

Serial

Input

A

B

C

D

Clock

Inhibit

Parallel

Inputs

Parallel

Inputs

Shift/Load

CK

Clock

Inhibit

A

B

C

D

Serial

Input

E

F

G

H