© 2005 Fairchild Semiconductor Corporation

DS011670

www.fairchildsemi.com

April 1994

Revised April 2005

74VHC273

Octal D-Type Flip-Flop

General Description

The VHC273 is an advanced high speed CMOS Octal

D-type flip-flop fabricated with silicon gate CMOS technol-

ogy. It achieves the high speed operation similar to equiva-

lent Bipolar Schottky TTL while maintaining the CMOS low

power dissipation.

The register has a common buffered Clock (CP) which is

fully edge-triggered. The state of each D input, one setup

time before the LOW-to-HIGH clock transition, is trans-

ferred to the corresponding flip-flop’s Q output. The Master

Reset (MR) input will clear all flip-flops simultaneously. All

outputs will be forced LOW independently of Clock or Data

inputs by a LOW voltage level on the MR input.

An input protection circuit insures that 0V to 7V can be

applied to the inputs pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery backup. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

s Power down protection is provided on all inputs

s Pin and function compatible with 74HC273

s Leadless DQFN Package

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Order Number

Package

Number

Package Description

74VHC273M

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC273SJ

M20D

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC273BQ

(Preliminary)

MLP020B

(Preliminary)

Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 4.5mm

74VHC273MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC273N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide