High-Current, 10

Analog Switches

8

_______________________________________________________________________________________

50%

0

LOGIC

INPUT

V-

-15V

NC

OR NO

GND

(

)

SWITCH

INPUT

IN

+3V

0

COM

SWITCH

OUTPUT

0.9V0

0.9V0

SWITCH

OUTPUT

SWITCH

INPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

V+

35pF

+15V

MAX4655–

MAX4658

Figure 3. Switching Time

Test Circuits/Timing Diagrams

TTL/CMOS

LEVEL

SHIFTER

NC

OR

NO

V+

IN

GND

V-

COM

SENSOR

NO OR

NC

COM

Figure 2. Block Diagram

VGEN

GND

NC OR

NO

CL

1nF

VO

-15V

V-

V+

VO

IN

OFF

ON

OFF

∆VO

Q = (

∆VO)(CL)

COM

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

MAX4655–

MAX4658

+15V

Figure 4. Charge Injection