SN54LV164A, SN74LV164A

8BIT PARALLELOUT SERIAL SHIFT REGISTERS

SCLS403H − APRIL 1998 − REVISED APRIL 2005

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

50% VCC

VCC

VCC

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VCC

0 V

50% VCC

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC

VOL + 0.3 V

50% VCC

≈0 V

VCC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST

S1

VCC

0 V

50% VCC

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPHL and tPLH are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

VCC

RL = 1 kΩ

GND

From Output

Under Test

CL

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

VOH − 0.3 V

Figure 1. Load Circuit and Voltage Waveforms