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K4M51323PC-SDG75 Datasheet(PDF) 7 Page - Samsung semiconductor

Part # K4M51323PC-SDG75
Description  Mobile-SDRAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K4M51323PC-SDG75 Datasheet(HTML) 7 Page - Samsung semiconductor

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K4M51323PC-S(D)E/G/C/F
February 2006
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Maximum burst refresh cycle : 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
Version
Unit
Note
-75
-90
-1L
Row active to row active delay
tRRD(min)
15
18
18
ns
1
RAS to CAS delay
tRCD(min)
22.5
24
27
ns
1
Row precharge time
tRP(min)
22.5
24
27
ns
1
Row active time
tRAS(min)
50
50
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
72.5
74
77
ns
1
Last data in to row precharge
tRDL(min)
15
ns
2
Last data in to Active delay
tDAL(min)
tRDL + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
80
ns
3
Exit self refresh to active command
tSRFX(min)
120
ns
Col. address to col. address delay
tCCD(min)
1
CLK
4
Number of valid output data
CAS latency=3
2
ea
5
Number of valid output data
CAS latency=2
1
Number of valid output data
CAS latency=1
-
0


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