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PLL1705DBQG4 Datasheet(PDF) 10 Page - Burr-Brown (TI) |
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PLL1705DBQG4 Datasheet(HTML) 10 Page - Burr-Brown (TI) |
10 / 18 page PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com 10 Table 3. Sampling Frequencies and System Clock Output Frequencies SAMPLING FREQUENCY (kHz) SAMPLING RATE SCKO2 (MHZ) SCKO3 (MHZ) 32 Standard 8.192 12.288 44.1 Standard 11.2896 16.9344 48 Standard 12.288 18.432 64 Double 16.384 24.576 88.2 Double 22.5792 33.8688 96 Double 24.576 36.864 Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from sampling frequency change to SCKO settling is 200 ns maximum. This clock transient timing is not synchronized with the SCKOx signals. Figure 10 illustrates SCKO transient timing in the PLL1706. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1705/6. SCKO0 SCKO1 200 ns SCKO2 SCKO3 ML Stable Clock Transition Region Stable 33.8688 MHz, 384 or 768 of 44.1 kHz 1–2 Clocks of MCKO1,2 Figure 10. System Clock Transient Timing POWER-ON RESET The PLL1705/6 has an internal power-on reset circuit. The mode register of PLL1706 is initialized with default settings by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power up time. Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on reset timing is shown in Figure 11. Reset Reset Removal 1024 Master Clocks VDD 2.4 V 2.0 V 1.6 V Internal Reset Master Clock Figure 11. Power-On Reset Timing |
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