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W83176R-735 Datasheet(PDF) 6 Page - Winbond |
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W83176R-735 Datasheet(HTML) 6 Page - Winbond |
6 / 13 page W83176R-735/W83176G-735 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET Publication Release Date: March 31, 2006 - 3 - Revision 1.1 4. PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin *- Internal 120k Ω pull-up 4.1 Clock Outputs SYMBOL PIN I/O FUNCTION CLKC[9:0] 26,30,40,43,4 7,23,19,9,6,2 OUT Complementory Clocks of differential pair outputs CLKT[9:0] 27,29,39,44,4 6,22,20,10,5,3 OUT True Clocks of differential pair outputs SDATA * 37 I/O Serial data of I 2C 2-wire control interface Internal pull-up resistor 120K to Vdd SCLK * 12 IN Serial clock of I 2C 2-wire control interface Internal pull-up resistor 120K to Vdd CLK_INT 13 IN True reference clock input, 3.3V tolerant input NC 14, 32,36 NONE Not connected FB_OUTT 33 OUT True Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. FB_INT 35 IN True Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. 4.2 Power Pins SYMBOL PIN FUNCTION GND 1,7,8,18,24,25,31,41,42,48 Ground VDD 4,11,15,21,28,34,38,45 Power Supply 2.5V AVDD 16 Analog power supply, 2.5V AGND 17 Analog ground |
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