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CS51311 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Voltage Identification DAC (continued) Line Regulation 9.0 V ≤ VCC ≤ 14 V − 0.01 − %/V Input Threshold VID4, VID3, VID2, VID1, VID0 1.0 1.25 2.4 V Input Pull−Up Resistance VID4, VID3, VID2, VID1, VID0 25 50 100 kΩ Pull−Up Voltage − 5.48 5.65 5.82 V Error Amplifier VFB Bias Current 0.2 V ≤ VFB ≤ 3.5 V −7.0 0.1 7.0 μA COMP Source Current VCOMP = 1.2 V to 3.6 V, VFB = 1.9 V 15 30 60 μA COMP Sink Current VCOMP = 1.2 V, VFB = 2.1 V 30 60 120 μA Open Loop Gain CCOMP = 0.1 μF − 80 − dB Unity Gain Bandwidth CCOMP = 0.1 μF − 50 − kHz PSRR @ 1.0 kHz CCOMP = 0.1 μF − 70 − dB Transconductance − − 32 − mmho Output Impedance − − 0.5 − MΩ GATE(H) and GATE(L) High Voltage at 100 mA Measure VCC − GATE(L)/(H) − 1.2 2.1 V Low Voltage at 100 mA Measure GATE(L)/(H) − 1.0 1.5 V Rise Time 1.6 V < GATE(H)/(L) < (VCC − 2.5 V) − 40 80 ns Fall Time (VCC − 2.5 V) > GATE(L)/(H) > 1.6 V − 40 80 ns GATE(H) to GATE(L) Delay GATE(H) < 2.0 V, GATE(L) > 2.0 V, VCC = 12 V 30 65 110 ns GATE(L) to GATE(H) Delay GATE(L) < 2.0 V, GATE(H) > 2.0 V, VCC = 12 V 30 65 110 ns GATE Pull−Down Resistance to GND. Note 3 20 50 115 kΩ Overcurrent Protection OVC Comparator Offset Voltage 0 V ≤ VOUT ≤ 3.5 V 77 86 101 mV Discharge Threshold Voltage − 0.2 0.25 0.3 V VOUT Bias Current 0.2 V ≤ VOUT ≤ 3.5 V −7.0 0.1 7.0 μA OVC Latch Discharge Current VCOMP = 1.0 V 100 800 2500 μA PWM Comparator PWM Comparator Offset Voltage 0 V ≤ VFB ≤ 3.5 V 0.99 1.1 1.23 V Transient Response VFB = 0 to 3.5 V − 200 300 ns COFF Off−Time − 1.0 1.6 2.3 μs Charge Current VCOFF = 1.5 V − 550 − μA Discharge Current VCOFF = 1.5 V − 25 − mA 3. Guaranteed by design, not 100% tested in production. |
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