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M41T94MQ6F Datasheet(PDF) 11 Page - STMicroelectronics |
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M41T94MQ6F Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 40 page  M41T94 Signal description 11/40 2 Signal description 2.1 Serial data output (SDO) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. 2.2 Serial data input (SDI) The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. 2.3 Serial clock (SCL) The serial clock provides the timing for the serial interface (as shown in Figure 7 on page 13 and Figure 8 on page 14). The W/R bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input. The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● (CPOL, CPHA) = ('0', '0') or ● (CPOL, CPHA) = ('1', '1'). For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10). 2.4 Chip Enable (E) When E is high, the memory device is deselected, and the SDO output pin is held in its high impedance state. After power-on, a high-to-low transition on E is required prior to the start of any operation. |
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