Electronic Components Datasheet Search |
|
MC10EL34 Datasheet(PDF) 6 Page - ON Semiconductor |
|
MC10EL34 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 8 page MC10EL34, MC100EL34 http://onsemi.com 6 There are two distinct functional relationships between the Master Reset and Clock: CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the outputs will follow the first ensuing clock rising edge. The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela- tionships. CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the outputs will follow the second ensuing clock rising edge. CASE 1 CASE 2 Figure 2. Timing Diagrams CLOCK OUTPUT MR TRR CLOCK OUTPUT MR TRR Figure 3. Reset Recovery Time CLK Q0 Q1 Q2 EN Internal Clock Disabled Internal Clock Enabled MR CLK Q0 Q1 Q2 EN Internal Clock Disabled Internal Clock Enabled MR |
Similar Part No. - MC10EL34_06 |
|
Similar Description - MC10EL34_06 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |