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MC100EL35DR2 Datasheet(PDF) 2 Page - ON Semiconductor

Part # MC100EL35DR2
Description  5V ECL JK Flip-Flop
Download  8 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EL35DR2 Datasheet(HTML) 2 Page - ON Semiconductor

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MC10EL35, MC100EL35
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. Logic Diagram and Pinout Assignment
K
Q
CLK
R
K
R
J
J
Table 1. PIN DESCRIPTION
PIN
FUNCTION
J
ECL Input
K
ECL Input
R
ECL Reset
CLK
ECL Clock Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed pad must be connected to a sufficient
thermal conduit. Electrically connect to the
most negative supply or leave floating open.
Table 1. TRUTH TABLE
J*
K*
R*
CLK
Qn+1
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Z
Z
Z
Z
X
Qn
L
H
Qn
L
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI  VCC
VI  VEE
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.


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